1. Field
The embodiments discussed herein are directed to a simulation method of a logic circuit including transistor circuit and custom macro circuit like RAM macro, devices, and a program for a timing analysis of the logic circuit.
2. Description of the Related Art
For a logic circuit containing a macro repeatedly used in an ultrahigh-speed LSI with a clock frequency of greater than several of GHz, an accurate timing analysis may be required at a phase of designing. One of the timing analysis conditions may be to analyze whether a circuit satisfies certain timing conditions. Based on a result of the timing analysis, a circuit such as a driver circuit may be selected. Conventionally, a method of the timing analysis, SPICE (Simulation Program with Integrated Circuit Emphasis), an industry standard simulation tool, has been used. However, the timing analysis with SPICE takes a lot of time, thus it is unpractical to conduct the analysis of a currently used logic circuit having a large number of transistors, e.g., several millions of transistors like RAM macro within a reasonable time.
Conventionally, there has been a timing analysis method that divide a circuit to be analyzed into small blocks, conduct simulations with SPICE for each divided block and then the results is stored in a library format, and then, conduct a static timing analysis (STA) on the whole circuit by using the created libraries for each block.
However, this conventional method is unable to obtain a satisfactory result on the analysis of a path required high degree of accuracy. In addition, since this analysis analyzes all paths of the circuit even where analyzing only a specific path. Thus, processing time becomes a bottleneck.